1. Field of Invention
This invention relates to methods for forming membrane structures for micro-devices, to the membrane structures themselves and to micro-devices including membrane structures.
2. Description of the Related Art
Various micro-devices are known that include a membrane structure are known. For example, fluid-handling micro-devices are known that use a membrane structure to control movement of a fluid. Exemplary micro-devices include micromachined fluid ejection devices for ink jet recording or printing, for depositing photoresist and other liquids in the semiconductor and flat panel display industries, for delivering drug and biological samples, for delivering multiple chemicals for chemical reactions, for handling DNA sequences, for delivering drugs and biological materials for interaction studies and assaying, or for depositing thin and narrow layers of plastics for usable as permanent and/or removable gaskets in micro-machines. See, for example, U.S. Pat. No. 6,127,198 to Coleman et al., incorporated herein by reference in its entirety.
Various fabrication techniques are known for such micro-devices, such as, surface and/or bulk micromachining techniques. Planar fabrication process steps common to the integrated circuit (IC) fabrication industry may be used to manufacture microelectromechanical or micromechanical devices. The standard building-block process consists of depositing and photolithographically patterning alternating layers on a substrate. The alternating layers consist of low-stress polycrystalline silicon (also termed polysilicon) and a sacrificial material such as silicon dioxide on a substrate. Vias etched through the sacrificial layers provide anchor points to the substrate and between the polysilicon layers. The polysilicon layers are patterned to form mechanical elements of the micromachined device. The mechanical elements are thus formed layer-by-layer in a series of deposition and patterning process steps. The silicon dioxide layers are then removed by exposure to a selective etchant, such as hydrofluoric acid (HF), which does not etch the polysilicon layers. This releases the mechanical elements formed in the polysilicon layers for movement thereof. Again, see the incorporated '198 patent, for example.
The resulting micromachined device generally consists of a first layer of polysilicon which provides electrical inter-connections and/or a voltage reference plane, and up to three additional layers of polysilicon which include mechanical elements ranging from simple cantilevered beams to complex systems, such as an electrostatic motor connected to a plurality of gears. Typical in-plane lateral dimensions can range from one micron to several hundred microns, while the layer thicknesses are typically about 0.5–2 microns. Because the entire process is based on standard IC fabrication technology, hundreds to thousands of devices can be batch-fabricated, fully assembled (without any need for piece-part assembly) on a single silicon substrate.
In particular, micro-devices may be fabricated using the SUMMiT processes. The SUMMiT processes are covered by various U.S. patents belonging to Sandia National Labs, including U.S. Pat. Nos. 5,783,340; 5,798,283; 5,804,084; 5,919,548; 5,963,788; and 6,053,208, each of which is incorporated herein by reference in its entirety. The SUMMiT processes are primarily covered by the '084 and '208 patents. In particular, the methods discussed in copending U.S. patent application Ser. No. 09/723,243 filed Nov. 28, 2000, incorporated herein by reference in its entirety, may be used.
A chemical mechanical polishing (CMP) technique that planarizes the various levels in a multilevel micromachined device to prevent unintended interference between structures on different layers of the micromachined device is described in U.S. Pat. No. 5,804,084 to Nasby et al. In the above-described process, as the relatively thick (2 μm) layers of polysilicon and oxide are deposited and etched, considerable surface topography arises which imposes limitations in deposition, patterning and etching of subsequent layers. The topography is created as the layers are draped into valleys created by prior etching steps. It is often desirable to planarize specific layers in order to eliminate processing difficulties associated with photoresist-step coverage, depth-of-focus of photolithography equipment, and stringer generation during dry etch. The chemical mechanical polishing of intermediate sacrificial layers as disclosed in U.S. Pat. No. 5,804,084 provides relatively simple and quick processing to ameliorate the topography difficulties inherent in multi-level micro-machining processes. This avoids the need for additional care in design of structures, special photoresist processes and the use of extra mask levels.
An anisotropic etching process may be used to define structures, for example trenches and ridges or the like having low to average selectivity, into silicon substrates. Individual structures to be etched in are usually defined by etching masks applied to the silicon substrate by way of so-called masking layers, for example, a photoresist layer. In the anisotropic etching technique, it is necessary to achieve a laterally exactly defined recess in the silicon. These deeply-extending recesses must have lateral ends which are as exactly vertical as possible. The edges of the masking layers covering those silicon substrate regions that are not supposed to be etched are not underetched in order to keep the lateral precision of the structural transition from the mask into the silicon as high as possible. As a result, it is necessary to allow the etching to progress only on the bottom of the structures, but not on the already produced side walls of the structures.
To this end, a plasma-etching method may be used to perform etching of profiles in silicon substrates. In such a method, chemically reactive species and electrically-charged particles (ions) are generated in a reactive gas mixture in a reactor with the aid of an electric discharge. The positively-charged cations generated in this manner are accelerated toward the substrate, by means of an electrical prestress applied to the silicon substrate, and fall virtually vertically onto the substrate surface, and promote the chemical reaction of the reactive plasma species with the silicon on the etching base.
A particular type of anisotropic etching process is described in U.S. Pat. No. 5,501,893 to Laermer et al. This particular type of etching process is commonly referred to as a Bosch etch. According to a Bosch etch, the anistropic etching process is achieved by alternating sequential etching and polymerization steps. As a consequence, in an advantageous manner the simultaneous presence of etching species and polymer formers in the plasma is avoided altogether. Hence, deep structures having vertical edges can be realized with very high etching rates in silicon substrates.